SH7020 Datasheet, PDF (348/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

• Bit 7 (watchdog timer overflow (WOVF)): WOVF indicates that the TCNT has overflowed
(H'FF → H'00) in the watchdog timer mode. It is not set in the interval timer mode.
Bit 7: WOVF
0
1
Description
No TCNT overflow in watchdog timer mode (initial value)
Cleared when software reads WOVF, then writes 0 in WOVF
Set by TCNT overflow in watchdog timer mode
• Bit 6 (reset enable (RSTE)): RSTE selects whether to reset the chip internally if the TCNT
overflows in the watchdog timer mode.
Bit 6: RSTE
0
1
Description
Not reset when TCNT overflows (initial value). LSI not reset internally,
but TCNT and TCSR reset within WDT.
Reset when TCNT overflows
• Bit 5 (reset select (RSTS)): RSTS selects the type of internal reset generated if the TCNT
overflows in the watchdog timer mode.
Bit 5: RSTS
0
1
Description
Power-on reset initial value)
Manual reset
• Bits 4–0 (reserved): These bits always read as 1. The write value should always be 1.
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