SH7020 Datasheet, PDF(111/509 Page) Renesas Technology Corp – SuperH™ RISC engine

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SH7020 Datasheet, PDF (111/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

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Section 8 Bus State Controller (BSC)

8.1 Overview

The bus state controller (BSC) divides address space and outputs control signals for all kinds of

memory and peripheral LSIs. BSC functions enable the LSI to link directly with DRAM, SRAM,

ROM, and peripheral LSIs without the use of external circuits, simplifying system design and

allowing high-speed data transfers in a compact system.

8.1.1 Features

The BSC has the following features.

â¢ Address space is divided into eight areas

ï£§ A maximum 4-Mbyte of linear address space for each of eight areas, 0â7 (area 1 can be up

to 16-Mbyte linear space when set for DRAM) (The space that can actually be used varies

with the type of memory connected)

ï£§ Bus width (8 bits or 16 bits) can be selected by access address

ï£§ On-chip ROM and RAM is accessed in one cycle (32 bits wide)

ï£§ Wait states can be inserted using the WAIT pin

ï£§ Wait state insertion can be controlled through software. Register settings can be used to

specify the insertion of 1â4 cycles for areas 0, 2, and 6 (long wait function)

ï£§ The type of memory connected can be specified for each area.

ï£§ Outputs control signals for accessing the memory and peripheral LSIs connected to the area

â¢ Direct interface to DRAM

ï£§ Multiplexes row/column addresses according to DRAM capacity

ï£§ Two types of byte access signals (dual-CAS system and dual-WE system)

ï£§ Supports burst operation (high-speed page mode)

ï£§ Supports CAS-before-RAS refresh and self-refresh

â¢ Access control for all memory and peripheral LSIs

ï£§ Address/data multiplex function

â¢ Parallel execution of external writes and the like with internal access (warp mode)

â¢ Supports parity check and generation for data bus

ï£§ Odd parity/even parity selectable

ï£§ Interrupt request generated for parity error (PEI interrupt request signal)

â¢ Refresh counter can be used as an 8-bit interval timer

ï£§ Interrupt request generated at compare match (CMI interrupt request signal)

8.1.2 Block Diagram

Figure 8.1 shows the block diagram of the bus state controller.

RENESAS 93

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