SH7020 Datasheet, PDF (116/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

Bit 14: IOE
0
1
Description
Area 6 is external memory space (initial value)
Area 6 is an address/data multiplexed I/O area
• Bit 13 (warp mode bit (WARP)): WARP selects warp or normal mode. 0 sets it for normal
mode and 1 sets it for warp mode. In warp mode, some external accesses are carried out in
parallel with internal access.
Bit 13: WARP
0
1
Description
Normal mode: External and internal accesses are not simultaneously
performed (initial value)
Warp mode: External and internal accesses are simultaneously
performed
• Bit 12 (RD duty (RDDTY)): RDDTY selects 35% or 50% of the T1 state as the high-level duty
cycle ratio of signal RD. 0 sets it for 50%, 1 sets it for 35%. Only set to 1 when the operating
frequency is a minimum of 10 MHz.
Bit 12: RDDTY
0
1
Description
RD signal high-level duty cycle is 50% of T1 state (initial value)
RD signal high-level duty cycle is 35% of T1 state
• Bit 11 (byte access select (BAS)): BAS selects whether byte access control signals are WRH,
WRL, and A0, or LBS, WR and HBS during word space accesses. When this bit is cleared to
0, WRH, WRL, and A0 signals are valid; when set to 1, LBS, WR, and HBS, signals are valid.
Bit 11: BAS
0
1
Description
WRH, WRL, and A0 enabled (initial value)
LBS, WR, and HBS enabled
• Bits 10–0 (reserved): These bits always read as 0. The write value should always be 0.
8.2.2 Wait State Control Register 1 (WCR1)
Wait state control register 1 is a 16-bit read/write register that controls the number of states for
accessing each area and the whether wait states are used. WCR1 is initialized to H'FFFF by a
power-on reset. It is not initialized by a manual reset or by the standby mode.
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