SH7020 Datasheet, PDF (195/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

• Bit 7 (acknowledge mode bit (AM)): In the dual address mode, AM selects whether the DACK
signal is output during the data read cycle or write cycle. This bit is valid only in channels 0
and 1. The AM bit is initialized to 0 by resets or in standby mode. The AM bit is not valid in
single address mode.
Bit 7: AM
0
1
Description
DACK is output in read cycle (initial value)
DACK is output in write cycle
• Bit 6 (acknowledge Level Bit (AL)): AL selects active high signal or active low signal for the
DACK signal. This bit is valid only in channels 0 and 1. The AL bit is initialized to 0 by resets
or in standby mode.
Bit 6: AL
0
1
Description
DACK is active high (initial value)
DACK is active low
• Bit 5 (DREQ select bit (DS)): DS selects the DREQ input detection method used. This bit is
valid only in channels 0 and 1. The DS bit is initialized to 0 by resets or in standby mode.
Bit 5: DS
0
1
Description
DREQ detected by low level (initial value)
DREQ detected by falling edge
• Bit 4 (transfer bus mode bit (TM)): TM selects the bus mode for DMA transfers. The TM bit is
initialized to 0 by resets or in standby mode. When the source of the transfer request is an on-
chip peripheral module, see table 9.4, Selecting On-Chip Peripheral Module Request Modes
with the RS Bit.
Bit 4: TM
Description
0
Cycle-steal mode (initial value)
1
Burst mode
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