SH7020 Datasheet, PDF (118/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

Table 8.3 Read Cycle State Description
Read Cycle States
External Memory Space
Internal space
WAIT
Bits 15–8: Pin Input External Memory
RW7–RW0 Signal Space
Multi- On-chip On-chip
Plexed Peripheral ROM and
DRAM Space I/O
Module RAM
0
Not
• Areas 1, 3–5,7: 1 Column add- 4 states 3 states, 1 state,
sampled state, fixed
ress cycle: 1 + wait fixed
fixed
during
read
cycle*¹
Areas 0, 2, 6: 1 state ^{state, fixed}
+ long wait state
(short pitch)
states
from
WAIT
1
Sampled Areas 1, 3–5, 7: 2 Column
during states + wait states address cycle:
read
from WAIT
2 states + wait
cycle
(initial
value)
Areas 0, 2, 6: 1 state ^{state from}
+ long wait state +
wait state from
WAIT (long
pitch)*²
WAIT
Notes: 1. Sampled in the address/data multiplexed I/O space
2. During a CBR refresh, the WAIT signal is ignored and the wait state from the RLW1
and RLW0 bits of RCR is inserted.
• Bits 7–2 (reserved): These bits always read as 1. The write value should always be 1.
• Bit 1 (wait state control during write (WW1)): WW1 determines the number of states in write
cycles for the DRAM space (area 1) and whether or not to sample the WAIT signal. When the
DRAM enable bit (DRAME) of the BCR is set to 1 and area 1 is being used as DRAM space,
clearing WW1 to 0 makes the column address output cycle finish in 1 states (short pitch).
When WW1 is set to 1, it finishes in 2 states plus the wait states from the WAIT signal (long
pitch).
Note: Write 0 to WW1 only when area 1 is used as DRAM space (DRAME bit of BCR is 1).
Never write 0 to WW1 when area 1 is used as external memory space (DRAME is 0).
Bit 1: WW1
0
1
DRAM Space (DRAME = 1)
Column address cycle: 1 state (short pitch)
Column address cycle: 2 states + wait state
from WAIT (long pitch) (initial value)
Area 1's External Memory
Space (DRAME = 0)
Setting inhibited
2 states + wait state from WAIT
• Bit 0 (reserved): This bit always reads 1. The write value should always be 1.
100 RENESAS