SH7020 Datasheet, PDF (146/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

8.4 Accessing External Memory Space
In external memory space, strobe signal is output based on the assumption of a directly connected
SRAM. The external memory space is allocated to the following areas:
• Area 0 (when MD2–MD0 are 000 or 001)
• Area 1 (when the DRAM enable bit (DRAME) of the BCR is 0)
• Areas 2–4
• Area 5 (space where address A27 is 1)
• Area 6 (when the multiplexed I/O enable bit (IOE) bit of the BCR is 0, or space where address
A27 is 1)
• Area 7 (space where address A27 is 0)
8.4.1 Basic Timing
The bus cycle for external memory space access is 1 or 2 states. The number of states is controlled
with the wait states by the settings of wait state control registers 1–3 (WCR1–WCR3). For details,
see section 8.4.2., Wait State Control. Figures 8.11 and 8.12 illustrate the basic timing of external
memory space access.
T1
CK
A21–A0
CSn
RD
(Read)
AD15–AD0
(Read)
Figure 8.11 Basic Timing of External Memory Space Access (1-state read timing)
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