SH7020 Datasheet, PDF (350/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

Writing to the RSTCSR: The RSTCSR must be written by a word access to address
H'5FFFFFBA. It cannot be written by byte transfer instructions. Procedures for writing 0 in
WOVF (bit 7) and for writing to RSTE (bit 6) and RSTS (bit 5) are different, as shown in figure
12.3. To write 0 in the WOVF bit, the write data must be H'A5 in the upper byte and H'00 in the
lower byte. This clears the WOVF bit to 0. The RSTE and RSTS bits are not affected. To write to
the RSTE and RSTS bits, the upper byte must be H'5A and the lower byte must be the write data.
The values of bits 6 and 5 of the lower byte are transferred to the RSTE and RSTS bits,
respectively. The WOVF bit is not affected.
Writing 0 to the WOVF bit
Address:
H'5FFFFBA
15
8
H'A5
7
0
H'00
Writing to the RSTE and RSTS bits
Address:
H'5FFFFBA
15
8
H'5A
7
0
Write data
Figure 12.3 Writing to the RSTCSR
Reading from the TCNT, TCSR, and RSTCSR: TCNT, TCSR, and RSTCSR are read like
other registers. Use byte transfer instructions. The read addresses are H'5FFFFB8 for the TCSR,
H'5FFFFB9 for the TCNT, and H'5FFFFBB for the RSTCSR.
12.3 Operation
12.3.1 Operation in the Watchdog Timer Mode
To use the WDT as a watchdog timer, set the WT/IT and TME bits of the TCSR to 1. Software
must prevent TCNT overflow by rewriting the TCNT value (normally by writing H'00) before
overflow occurs. If the TCNT fails to be rewritten and overflows due to a system crash or the like,
a WDTOVF signal is output (figure 12.4). The WDTOVF signal can be used to reset external
system devices. The WDTOVF signal is output for 128φ clock cycles.
If the RSTE bit in the RSTCSR is set to 1, a signal to reset the chip will be generated internally
simultaneous to the WDTOVF signal when TCNT overflows. Either a power-on reset or a manual
reset can be selected by the RSTS bit. The internal reset signal is output for 512φ clock cycles.
When a watchdog reset is generated simultaneously with input at the RES pin, the software
distinguishes the RES reset from the watchdog reset by checking the WOVF bit in the RSTCSR.
The RES reset takes priority. The WOVF bit is cleared to 0.
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