SH7020 Datasheet, PDF (232/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

10.1.2 Block Diagram
ITU Block Diagram (Complete): Figure 10.1 is the block diagram of the ITU.
TCLKA–TCLKD
φ, φ/2, φ/4, φ/8
TOCXA4, TOCXB4
TIOCA0–TIOCA4
TIOCB0–TIOCB4
Clock
selection
Control
logic
Counter control and
pulse I/O control unit
IMIA0–IMIA4
IMIB0–IMIB4
OVI0–OVI4
TOCR
TSTR
TSNC
TMDR
TFCR
Internal
data
bus
Module data bus
TOCR: Timer output control register (8 bits)
TSTR: Timer start regsiter (8 bits)
TSNC: Timer synchronization register (8 bits)
TMDR: Timer mode register (8 bits)
TFCR: Timer function control register (8 bits)
Figure 10.1 ITU Block Diagram
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