SH7020 Datasheet, PDF (102/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

BARH/BARL
BAMRH/BAMRL
Internal address
bits 31–0
CD1
32
32
CD0
32
32
32
CPU cycle
DMA cycle
ID1 ID0
Instruction fetch
Data access
RW1 RW0
Read cycle
User
break
interrupt
Write cycle
SZ1 SZ0
Byte size
Word size
Long word size
Figure 6.2 Break Condition Logic
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