SH7020 Datasheet, PDF (308/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

10.6.8 Contention between General Register Write and Input Capture
If an input capture signal is generated during the T3 state of a general register write cycle, the
input capture transfer takes priority and the write to the GR is not performed. The timing is shown
in figure 10.65.
GR write cycle
T1
T2
T3
CK
Address
Internal
write signal
Input capture
signal
TCNT
GR address
M
GR
M
Figure 10.65 Contention between General Register Write and Input Capture
10.6.9 Note on Waveform Cycle Setting
When a counter is cleared by compare match, the counter is cleared in the last state in which the
TCNT value matches the GR value (when the TCNT is updated from the matching count to the
next count). The actual counter frequency is therefore given by the following formula:
f = φ/(N + 1)
(f: counter frequency. φ: operating frequency. N: value set in the GR.)
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