SH7125_08 Datasheet, PDF (98/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 5 Exception Handling
5.3.2 Address Error Exception Source
When an address error exception is generated, the bus cycle which caused the address error ends,
the current instruction finishes, and then the address error exception handling starts. The CPU
operates as follows:
1. The status register (SR) is saved to the stack.
2. The program counter (PC) is saved to the stack. The PC value to be saved is the start address
of the instruction which caused an address error exception. When the instruction that caused
the exception is placed in the delay slot, the address of the delayed branch instruction which is
placed immediately before the delay slot.
3. The start address of the exception handling routine is fetched from the exception handling
vector table that corresponds to the generated address error, and the program starts executing
from that address. This branch is not a delayed branch.
Rev. 4.00 Jul. 25, 2008 Page 78 of 750
REJ09B0243-0400