SH7125_08 Datasheet, PDF (500/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 13 A/D Converter (ADC)
Initial
Bit Bit Name Value
R/W
14
ADIE
0
R/W
13, 12 
All 0
R
11
TRGE
0
R/W
10

0
R
9
CONADF 0
R/W
Description
A/D Interrupt Enable
The A/D conversion end interrupt (ADI) request is
enabled when 1 is set
When changing the operating mode, first clear the
ADST bit to 0.
Reserved
These bits are always read as 0. The write value
should always be 0.
Trigger Enable
Enables or disables triggering of A/D conversion by
ADTRG and an MTU2 trigger.
0: A/D conversion triggering is disabled
1: A/D conversion triggering is enabled
When changing the operating mode, first clear the
ADST bit to 0.
Reserved
This bit is always read as 0. The write value should
always be 0.
ADF Control
Controls setting of the ADF bit in 2-channel scan
mode. The setting of this bit is valid only when
triggering of A/D conversion is enabled (TRGE = 1) in
2-channel scan mode. The setting of this bit is ignored
in single mode or 4-channel scan mode.
0: The ADF bit is set when A/D conversion started by
the group 0 trigger or group 1 trigger has finished.
1: The ADF bit is set when A/D conversion started by
the group 0 trigger and A/D conversion started by
the group 1 trigger have both finished. Note that the
triggering order has no affect.
When changing the operating mode, first clear the
ADST bit to 0.
Rev. 4.00 Jul. 25, 2008 Page 480 of 750
REJ09B0243-0400