SH7125_08 Datasheet, PDF (573/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 16 I/O Ports
16.1.1 Register Descriptions
Port A is a 16-bit input/output port in the SH7125 and an 8-bit input/output port in the SH7124.
Port A has the following registers. For details on register addresses and register states during each
processing, refer to section 20, List of Registers.
Table 16.1 Register Configuration
Register Name
Port A data register L
Port A port register L
Abbrevia-
tion
R/W Initial Value Address
Access Size
PADRL
R/W H'0000
H'FFFFD102 8, 16
PAPRL
R

H'FFFFD11E 8, 16
16.1.2 Port A Data Register L (PADRL)
PADRL is a 16-bit readable/writable register that stores port A data. Bits PA15DR to PA0DR
correspond to pins PA15 to PA0 (multiplexed functions omitted here) in the SH7125. Bits PA9DR
to PA6DR, PA4DR, PA3DR, PA1DR, and PA0DR correspond to pins PA9 to PA6, PA4, PA3,
PA1, and PA0, respectively (multiplexed functions omitted here) in the SH7124.
When a pin function is general output, if a value is written to PADRL, that value is output directly
from the pin, and if PADRL is read, the register value is returned directly regardless of the pin
state.
When a pin function is general input, if PADRL is read, the pin state, not the register value, is
returned directly. If a value is written to PADRL, although that value is written into PADRL, it
does not affect the pin state. Table 16.2 summarizes port A data register read/write operations.
Rev. 4.00 Jul. 25, 2008 Page 553 of 750
REJ09B0243-0400