SH7125_08 Datasheet, PDF (402/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 10 Port Output Enable (POE)
Figure 10.1 shows a block diagram of the POE.
TIOC3B
TIOC3D
TIOC4A
TIOC4C
TIOC4B
TIOC4D
POE3 *
POE1
POE0
Output level comparison circuit
Output level comparison circuit
Output level comparison circuit
Input level detection circuit
Falling edge
detection circuit
Low level
sampling circuit
POECR1,
POECR2
High-impedance
request signal for MTU2
high-current pins
High-impedance
request signal for MTU2
channel 0 pins
Interrupt
request signal
POE8
Input level detection circuit
Falling edge
detection circuit
Low level
sampling circuit
[Legend]
ICSR1: Input level control/status register 1
ICSR3: Input level control/status register 3
OCSR1: Output level control/status register 1
POECR1: Port output enable control register 1
POECR2: Port output enable control register 2
SPOER: Software port output enable register
Note: * This pin is supported only by the SH7125.
Pφ/8
Pφ/16
Pφ/128
Frequency
divider
Pφ
SPOER
Figure 10.1 Block Diagram of POE
Rev. 4.00 Jul. 25, 2008 Page 382 of 750
REJ09B0243-0400