SH7125_08 Datasheet, PDF (428/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 11 Watchdog Timer (WDT)
11.4 Operation
11.4.1 Canceling Software Standbys
The WDT can be used to revoke software standby mode with an NMI interrupt or external
interrupt (IRQ). The procedure is described below. (The WDT does not run when resets are used
for canceling, so keep the RES pin low until the clock stabilizes.)
1. Before transition to software standby mode, always clear the TME bit in WTCSR to 0. When
the TME bit is 1, an erroneous reset or interval timer interrupt may be generated when the
count overflows.
2. Set the type of count clock used in the CKS2 to CKS0 bits in WTCSR and the initial values for
the counter in the WTCNT counter. These values should ensure that the time till count
overflow is longer than the clock oscillation settling time.
3. Transition to software standby mode by executing a SLEEP instruction to stop the clock.
4. The WDT starts counting by detecting a change in the level input to the NMI or IRQ pin.
5. When the WDT count overflows, the CPG starts supplying the clock and the LSI resumes
operation. The WOVF flag in WTCSR is not set when this happens.
11.4.2 Using Watchdog Timer Mode
While operating in watchdog timer mode, the WDT generates an internal reset of the type
specified by the RSTS bit in WTCSR and asserts a signal through the WDTOVF pin every time
the counter overflows.
1. Set the WT/IT bit in WTCSR to 1, set the reset type in the RSTS bit, set the type of count
clock in the CKS2 to CKS0 bits, and set the initial value of the counter in the WTCNT
counter.
2. Set the TME bit in WTCSR to 1 to start the count in watchdog timer mode.
3. While operating in watchdog timer mode, rewrite the counter periodically to prevent the
counter from overflowing.
4. When the counter overflows, the WDT sets the WOVF flag in WTCSR to 1, asserts a signal
through the WDTOVF pin for one cycle of the count clock specified by the CKS2 to CKS0
bits, and generates a reset of the type specified by the RSTS bit. The counter then resumes
counting.
Rev. 4.00 Jul. 25, 2008 Page 408 of 750
REJ09B0243-0400