SH7125_08 Datasheet, PDF (489/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 12 Serial Communication Interface (SCI)
12.5 SCI Interrupt Sources
The SCI has four interrupt sources: transmit end (TEI), receive error (ERI), receive-data-full
(RXI), and transmit-data-empty (TXI) interrupt requests.
Table 12.17 shows the interrupt sources. The interrupt sources are enabled or disabled by means of
the TIE, RIE, and TEIE bits in SCSCR and the EIO bit in SCSPTR. A separate interrupt request is
sent to the interrupt controller for each of these interrupt sources.
When the TDRE flag in the serial status register (SCSSR) is set to 1, a TDR empty interrupt
request is generated. When the RDRF flag in SCSSR is set to 1, an RDR full interrupt request is
generated. When the ORER, FER, or PER flag in SCSSR is set to 1, an ERI interrupt request is
generated. When the TEND flag in SCSSR is set to 1, a TEI interrupt request is generated.
The TXI interrupt indicates that transmit data can be written, and the TEI interrupt indicates that
transmission has been completed.
Table 12.17 SCI Interrupt Sources
Interrupt Source Description
ERI
Interrupt caused by receive error (ORER, FER, or PER)
RXI
Interrupt caused by receive data full (RDRF)
TXI
Interrupt caused by transmit data empty (TDRE)
TEI
Interrupt caused by transmit end (TENT)
Rev. 4.00 Jul. 25, 2008 Page 469 of 750
REJ09B0243-0400