SH7125_08 Datasheet, PDF (505/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 13 A/D Converter (ADC)
13.3.4 A/D Trigger Select Register_0 (ADTSR_0)
The ADTSR_0 enables an A/D conversion started by an external trigger signal.
In particular, the four channels in A/D module 0 are divided into two groups (group 0 and group 1)
and the A/D trigger can be specified for each group independently in 2-channel scan mode.
Bit: 15
Initial value: 0
R/W: R/W
14 13
TRG11S[3:0]
0
0
R/W R/W
12
0
R/W
11
0
R/W
10 9
TRG01S[3:0]
0
0
R/W R/W
8
0
R/W
7
0
R/W
6
5
TRG1S[3:0]
0
0
R/W R/W
4
0
R/W
3
0
R/W
2
1
TRG0S[3:0]
0
0
R/W R/W
0
0
R/W
Initial
Bit
Bit Name Value
15 to 12 TRG11S[3:0] 0000
R/W Description
R/W A/D Trigger 1 Group 1 Select 3 to 0
Select an external trigger or MTU2 trigger to start A/D
conversion for group 1 when A/D module 1 is in 2-
channel scan mode.
0000: External trigger pin (ADTRG) input
0001: TRGA input capture/compare match for each
MTU2 channel or TCNT_4 underflow (trough) in
complementary PWM mode (TRGAN)
0010: MTU2 channel 0 compare match (TRG0N)
0011: MTU2 A/D conversion start request delaying
(TRG4AN)
0100: MTU2 A/D conversion start request delaying
(TRG4BN)
0101: Setting prohibited
0110: Setting prohibited
0111: Setting prohibited
1xxx: Setting prohibited
When switching the selector, first clear the ADST bit in
the A/D control register (ADCR) to 0.
Specify different trigger sources for the group 0 and
group 1 conversion requests so that a group 0
conversion request is not generated simultaneously
with a group 1 conversion request in 2-channel scan
mode.
Rev. 4.00 Jul. 25, 2008 Page 485 of 750
REJ09B0243-0400