SH7125_08 Datasheet, PDF(79/774 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

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SH7125_08 Datasheet, PDF (79/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

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Section 4 Clock Pulse Generator (CPG)

4.3 Clock Operating Mode

Table 4.3 shows the clock operating mode of this LSI.

Table 4.3 Clock Operating Mode

Source

PLL Circuit

EXTAL input or crystal resonator ON (Ã8)

Input to Divider

Ã8

The frequency of the external clock input from the EXTAL pin is multiplied by 8 in the PLL

circuit before being supplied to the on-chip modules in this LSI, which eliminates the need to

generate a high-frequency clock outside the LSI. Since the input clock frequency ranging from 10

MHz to 12.5 MHz can be used, the internal clock (IÏ) frequency ranges from 10 MHz to 50 MHz.

Maximum operating frequencies:

IÏ = 50 MHz, BÏ = 40 MHz, PÏ = 40 MHz, and MPÏ = 40 MHz

Table 4.4 shows the frequency division ratios that can be specified with FRQCR.

Rev. 4.00 Jul. 25, 2008 Page 59 of 750

REJ09B0243-0400

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