SH7125_08 Datasheet, PDF (23/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 1 Overview
Items
Interrupt controller
(INTC)
User debugging
interface (H-UDI)
Clock pulse
generator (CPG)
Watchdog timer
(WDT)
Specification
• External interrupt pins
 SH7125: Five pins (NMI and IRQ3 to IRQ0)
 SH7124: Four pins (NMI and IRQ3 to IRQ1)
• On-chip peripheral interrupts: Priority level set for each module
• Vector addresses: A vector address for each interrupt source
• E10A emulator support
• Clock mode: Input clock can be selected from external input or crystal
resonator
• Four types of clocks generated:
 CPU clock: Maximum 50 MHz
 Bus clock: Maximum 40 MHz
 Peripheral clock: Maximum 40 MHz
 MTU2 clock: Maximum 40 MHz
• On-chip one-channel watchdog timer
• Interrupt generation is supported.
Rev. 4.00 Jul. 25, 2008 Page 3 of 750
REJ09B0243-0400