SH7125_08 Datasheet, PDF (625/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 17 Flash Memory
Initial
Bit
Bit Name Value
R/W Description
6
MD
Undefined R/W Erasure Mode Related Setting Error Detect
Returns the check result of whether the signal input to
the FWE pin is high and whether the error protection
state is not entered.
When a low-level signal is input to the FWE pin or the
error protection state is entered, 1 is written to this bit.
The input level to the FWE pin and the error protection
state can be confirmed with the FWE bit (bit 7) and the
FLER bit (bit 4) in FCCS, respectively. For conditions to
enter the error protection state, see section 17.6.3,
Error Protection.
0: FWE and FLER settings are normal (FWE = 1, FLER
= 0)
1: FWE = 0 or FLER = 1, and erasure cannot be
performed
5
EE
Undefined R/W Erasure Execution Error Detect
1 is returned to this bit when the user MAT could not be
erased or when flash-memory related register settings
are partially changed on returning from the user branch
processing.
If this bit is set to 1, there is a high possibility that the
user MAT is partially erased. In this case, after
removing the error factor, erase the user MAT.
0: Erasure has ended normally
1: Erasure has ended abnormally (erasure result is not
guaranteed)
4
FK
Undefined R/W Flash Key Register Error Detect
Returns the check result of FKEY value before start of
the erasing processing.
0: FKEY setting is normal (FKEY = H'5A)
1: FKEY setting is error (FKEY = value other than H'5A)
3
EB
Undefined R/W Erase Block Select Error Detect
Returns the check result whether the specified erase-
block number is in the block range of the user MAT.
0: Setting of erase-block number is normal
1: Setting of erase-block number is abnormal
Rev. 4.00 Jul. 25, 2008 Page 605 of 750
REJ09B0243-0400