SH7125_08 Datasheet, PDF (482/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 12 Serial Communication Interface (SCI)
Start of transmission and reception
Read TDRE flag in SCSSR
No
TDRE = 1?
Yes
Write transmit data to SCTDR and
clear TDRE flag in SCSSR to 0
Read ORER flag in SCSSR
ORER = 1?
No
Yes
Error processing
Read RDRF flag in SCSSR
No
RDRF = 1?
Yes
Write transmit data to SCTDR, and
clear TDRE flag in SCSSR to 0
[1] SCI status check and transmit data write:
Read SCSSR and check that the TDRE flag is
set to 1, then write transmit data to SCTDR and
clear the TDRE flag to 0.
Transition of the TDRE flag from 0 to 1 can also
be identified by a TXI interrupt.
[2] Receive error processing:
If a receive error occurs, read the ORER flag in
SCSSR, and after performing the appropriate
error processing, clear the ORER flag to 0.
Reception cannot be resumed if the ORER flag
is set to 1.
[3] SCI status check and receive data read:
Read SCSSR and check that the RDRF flag is
set to 1, then read the receive data in SCRDR
and clear the RDRF flag to 0. Transition of the
RDRF flag from 0 to 1 can also be identified by
an RXI interrupt.
[4] Serial transmission/reception continuation
procedure:
To continue serial transmission/reception,
before the MSB (bit 7) of the current frame is
received, finish reading the RDRF flag, reading
SCRDR, and clearing the RDRF flag to 0. Also,
before the MSB (bit 7) of the current frame is
transmitted, read 1 from the TDRE flag to
confirm that writing is possible. Then write data
to SCTDR and clear the TDRE flag to 0.
No
All data received?
Yes
Clear TE and RE bits in SCSCR to 0
End of transmission and reception
Note: When switching from transmit or receive operation to simultaneous transmit and receive operations, first clear the
TE bit and RE bit to 0, then set both these bits to 1 simultaneously.
Figure 12.14 Sample Flowchart for Transmitting/Receiving Serial Data
Rev. 4.00 Jul. 25, 2008 Page 462 of 750
REJ09B0243-0400