SH7125_08 Datasheet, PDF (408/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 10 Port Output Enable (POE)
Initial
Bit Bit Name value R/W Description
1, 0 POE0M[1:0] 00
R/W*² POE0 mode 1, 0
These bits select the input mode of the POE0 pin.
00: Accept request on falling edge of POE0 input
01: Accept request when POE0 input has been sampled
for 16 Pφ/8 clock pulses and all are low level.
10: Accept request when POE0 input has been sampled
for 16 Pφ/16 clock pulses and all are low level.
11: Accept request when POE0 input has been sampled
for 16 Pφ/128 clock pulses and all are low level.
Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
2. Can be modified only once after a power-on reset.
10.3.2 Output Level Control/Status Register 1 (OCSR1)
OCSR1 is a 16-bit readable/writable register that controls the enable/disable of both output level
comparison and interrupts, and indicates status.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
OSF1 -
-
-
-
- OCE1 OIE1 -
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W:R/(W)*¹ R
R
R
R
R R/W*² R/W R
R
R
R
R
R
R
R
Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
2. Can be modified only once after a power-on reset.
Initial
Bit
Bit Name value R/W Description
15
OSF1
0
R/(W)*¹ Output Short Flag 1
This flag indicates that any one of the three pairs of
MTU2 2-phase outputs to be compared has
simultaneously become an active level.
[Clearing condition]
• By writing 0 to OSF1 after reading OSF1 = 1
[Setting condition]
• When any one of the three pairs of 2-phase outputs
has simultaneously become an active level
Rev. 4.00 Jul. 25, 2008 Page 388 of 750
REJ09B0243-0400