SH7125_08 Datasheet, PDF (182/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2)
9.3.1 Timer Control Register (TCR)
The TCR registers are 8-bit readable/writable registers that control the TCNT operation for each
channel. The MTU2 has a total of eight TCR registers, one each for channels 0 to 4 and three
(TCRU_5, TCRV_5, and TCRW_5) for channel 5. TCR register settings should be conducted
only when TCNT operation is stopped.
Bit: 7
6
5
CCLR[2:0]
Initial value: 0
0
0
R/W: R/W R/W R/W
4
3
CKEG[1:0]
0
0
R/W R/W
2
1
0
TPSC[2:0]
0
0
0
R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
7 to 5 CCLR[2:0] 000
R/W Counter Clear 0 to 2
These bits select the TCNT counter clearing source.
See tables 9.4 and 9.5 for details.
4, 3 CKEG[1:0] 00
R/W Clock Edge 0 and 1
These bits select the input clock edge. When the input
clock is counted using both edges, the input clock
period is halved (e.g. MPφ/4 both edges = MPφ/2 rising
edge). If phase counting mode is used on channels 1
and 2, this setting is ignored and the phase counting
mode setting has priority. Internal clock edge selection
is valid when the input clock is MPφ/4 or slower. When
MPφ/1, or the overflow/underflow of another channel is
selected for the input clock, although values can be
written, counter operation compiles with the initial value.
00: Count at rising edge
01: Count at falling edge
1x: Count at both edges
2 to 0 TPSC[2:0] 000
R/W Time Prescaler 0 to 2
These bits select the TCNT counter clock. The clock
source can be selected independently for each channel.
See tables 9.6 to 9.10 for details.
[Legend]
x: Don't care
Rev. 4.00 Jul. 25, 2008 Page 162 of 750
REJ09B0243-0400