SH7125_08 Datasheet, PDF (94/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 5 Exception Handling
Exception Handling Source
Vector Number Vector Table Address Offset
Interrupt
IRQ0 (SH7125)
64
H'00000100 to H'00000103
IRQ1
65
H'00000104 to H'00000107
IRQ2
66
H'00000108 to H'0000010B
IRQ3
67
H'0000010C to H'0000010F
(Reserved for system use)
68
H'00000110 to H'00000113
:
:
71
H'0000011C to H'0000011F
On-chip peripheral module*
72
H'00000120 to H'00000123
:
:
255
H'000003FC to H'000003FF
Note: * For details on the vector numbers and vector table address offsets of on-chip peripheral
module interrupts, see table 6.3 in section 6, Interrupt Controller (INTC).
Table 5.4 Calculating Exception Handling Vector Table Addresses
Exception Source
Vector Table Address Calculation
Resets
Vector table address = (vector table address offset)
= (vector number) × 4
Address errors, interrupts,
instructions
Vector table address = VBR + (vector table address offset)
= VBR + (vector number) × 4
Notes: 1. VBR: Vector base register
2. Vector table address offset: See table 5.3.
3. Vector number: See table 5.3.
Rev. 4.00 Jul. 25, 2008 Page 74 of 750
REJ09B0243-0400