SH7125_08 Datasheet, PDF (110/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Interrupt Controller (INTC)
Figure 6.1 shows a block diagram of the INTC.
IRQOUT
NMI
IRQ0 *
IRQ1
IRQ2
IRQ3
Input
control
UBC
WDT
CMT
MTU2
A/D
SCI
POE
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
Com-
parator
Interrupt
request
SR
I3 I2 I1 I0
CPU
ICR0
IRQCR
IRQSR
IPR
IPRA to IPRF,
IPRH to IPRM
Module bus
Bus
interface
[Legend]
UBC:
WDT:
CMT:
User break controller
Watchdog timer
Compare match timer
SCI: Serial communication interface
MTU2: Multi-function timer pulse unit 2
A/D: A/D converter
POE: Port output enable
Note: Supported only by the SH7125.
INTC
ICR0:
IRQCR:
IRQSR:
IPRA to IPRF,
IPRH to IPRM:
SR:
Interrupt control register 0
IRQ control register
IRQ status register
Interrupt priority registers A to F and H to M
Status register
Figure 6.1 Block Diagram of INTC
Rev. 4.00 Jul. 25, 2008 Page 90 of 750
REJ09B0243-0400