SH7125_08 Datasheet, PDF (430/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 11 Watchdog Timer (WDT)
11.5 Usage Note
If WTCNT is set to H'FF in interval timer mode, overflow does not occur when WTCNT reaches
the immediate H'00, but occurs when WTCNT changes from H'FF to H'00 after 257 cycles of
count clock.
Whereas if WTCNT is set to H'FF in watchdog timer mode, overflow occurs when WTCNT
changes from H'FF to H'00 after one cycle of count clock.
Rev. 4.00 Jul. 25, 2008 Page 410 of 750
REJ09B0243-0400