SH7125_08 Datasheet, PDF (526/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 14 Compare Match Timer (CMT)
Initial
Bit
Bit Name value R/W Description
15 to 8 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
7
CMF
0
R/(W)*¹ Compare Match Flag
Indicates whether or not the values of CMCNT and
CMCOR match.
0: CMCNT and CMCOR values do not match
[Clearing condition]
• When 0 is written to this bit after reading CMF = 1*²
[Setting condition]
1: CMCNT and CMCOR values match
6
CMIE
0
R/W Compare Match Interrupt Enable
Enables or disables compare match interrupt (CMI)
generation when CMCNT and CMCOR values match
(CMF=1).
0: Compare match interrupt (CMI) disabled
1: Compare match interrupt (CMI) enabled
5 to 2 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
1, 0
CKS[1:0] 00
R/W Clock Select 1 and 0
Select the clock to be input to CMCNT from four internal
clocks obtained by dividing the peripheral operating
clock (Pφ). When the STR bit in CMSTR is set to 1,
CMCNT starts counting on the clock selected with bits
CKS1 and CKS0.
00: Pφ/8
01: Pφ/32
10: Pφ/128
11: Pφ/512
Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
2. If another flag setting condition occurs before writing 0 to the bit after reading it as 1, the
flag will not be cleared by simply writing 0 to it. In this case, read the bit as 1 once again
and write 0 to it.
Rev. 4.00 Jul. 25, 2008 Page 506 of 750
REJ09B0243-0400