SH7125_08 Datasheet, PDF (350/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2)
TCFV Flag/TCFU Flag Setting Timing: Figure 9.103 shows the timing for setting of the TCFV
flag in TSR on overflow, and TCIV interrupt request signal timing.
Figure 9.104 shows the timing for setting of the TCFU flag in TSR on underflow, and TCIU
interrupt request signal timing.
MPφ, Pφ
TCNT input
clock
TCNT
(overflow)
Overflow
signal
TCFV flag
H'FFFF
H'0000
TCIV interrupt
Figure 9.103 TCIV Interrupt Setting Timing
MPφ, Pφ
TCNT
input clock
TCNT
(underflow)
Underflow
signal
TCFU flag
H'0000
H'FFFF
TCIU interrupt
Figure 9.104 TCIU Interrupt Setting Timing
Rev. 4.00 Jul. 25, 2008 Page 330 of 750
REJ09B0243-0400