SH7125_08 Datasheet, PDF (356/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2)
9.7.7 Contention between Buffer Register Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR
by the buffer operation is the data before write.
Figure 9.111 shows the timing in this case.
TGR write cycle
T1
T2
MPφ
Address
Write signal
Compare match
signal
Compare match
buffer signal
Buffer register
Buffer register
address
Buffer register write data
N
M
TGR
N
Figure 9.111 Contention between Buffer Register Write and Compare Match
Rev. 4.00 Jul. 25, 2008 Page 336 of 750
REJ09B0243-0400