SH7125_08 Datasheet, PDF (354/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2)
9.7.5 Contention between TCNT Write and Increment Operations
If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence
and TCNT is not incremented.
Figure 9.109 shows the timing in this case.
MPφ
TCNT write cycle
T1 T2
Address
TCNT address
Write signal
TCNT input
clock
TCNT
N
M
TCNT write data
Figure 9.109 Contention between TCNT Write and Increment Operations
Rev. 4.00 Jul. 25, 2008 Page 334 of 750
REJ09B0243-0400