SH7125_08 Datasheet, PDF (330/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2)
Note:
This function must be used in combination with interrupt skipping.
When interrupt skipping is disabled (the T3AEN and T4VEN bits in the timer interrupt
skipping set register (TITCR) are cleared to 0 or the skipping count set bits (3ACOR and
4VCOR) in TITCR are cleared to 0), make sure that A/D converter start requests are not
linked with interrupt skipping (clear the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in
the timer A/D converter start request control register (TADCR) to 0).
TADCORA_4
TCNT_4
TGIA_3 interrupt
skipping counter
TCIV_4 interrupt
skipping counter
00
00
01
01
02
02
00
00
01
01
TGIA_3 A/D request-enabled
period
TCIV_4 A/D request-enabled
period
A/D converter start request (TRG4AN)
When linked with TGIA_3 and TCIV_4
interrupt skipping
When linked with TGIA_3
interrupt skipping
When linked with TCIV_4
interrupt skipping
Note: * When the interrupt skipping count is set to two.
(UT4AE/DT4AE = 1)
Figure 9.75 Example of A/D Converter Start Request Signal (TRG4AN) Operation Linked
with Interrupt Skipping
Rev. 4.00 Jul. 25, 2008 Page 310 of 750
REJ09B0243-0400