SH7125_08 Datasheet, PDF (275/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2)
Figure 9.27 shows an example of PWM mode 2 operation in the SH7125.
In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare
match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the
output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), outputting a 5-phase
PWM waveform.
In this case, the value set in TGRB_1 is used as the cycle, and the values set in the other TGRs are
used as the duty levels.
TCNT value
TGRB_1
TGRA_1
TGRD_0
TGRC_0
TGRB_0
TGRA_0
H'0000
TIOC0A
Counter cleared by
TGRB_1 compare match
TIOC0B
TIOC0C
TIOC0D
TIOC1A
Figure 9.27 Example of PWM Mode Operation (2)
Time
Rev. 4.00 Jul. 25, 2008 Page 255 of 750
REJ09B0243-0400