SH7125_08 Datasheet, PDF (769/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

S
SCI interrupt sources .............................. 469
SCSPTR and SCI pins ............................ 470
Sending a break signal ............................ 472
Sequential break ..................................... 137
Serial communication interface (SCI) .... 411
Shift instructions....................................... 42
Single chip mode ...................................... 50
Single mode ............................................ 489
Single-cycle scan mode .......................... 490
Sleep mode ............................................. 671
Software protection................................. 621
Software standby mode........................... 672
Stack after interrupt exception
handling .................................................. 110
Stack states after exception
handling ends............................................ 84
Status register (SR)................................... 19
System control instructions....................... 44
T
Target pins and conditions for high-
impedance control................................... 396
The address map for the operating modes. 51
Trap instructions ....................................... 81
U
User break controller (UBC)................... 113
User break interrupt ................................ 103
User MAT ............................................... 580
User program mode................................. 611
Using interval timer mode....................... 409
Using watchdog timer mode ................... 408
V
Vector numbers and vector table
address offsets........................................... 73
Vector-base register (VBR) ...................... 20
W
Watchdog timer (WDT) .......................... 401
Rev. 4.00 Jul. 25, 2008 Page 749 of 750
REJ09B0243-0400