SH7125_08 Datasheet, PDF (553/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 15 Pin Function Controller (PFC)
15.1.3 Port B I/O Registers L and H (PBIORL and PBIORH)
PBIORL and PBIORH are 16-bit readable/writable registers that are used to set the pins on port B
as inputs or outputs. Bits PB16IOR, PB5IOR, and PB3IOR to PB1IOR correspond to pins PB16,
PB5, and PB3 to PB1, respectively (names of multiplexed pins are here given as port names and
pin numbers alone). PBIORL is enabled when the port B pins are functioning as general-purpose
inputs/outputs (PB5 and PB3 to PB1), and the SCK pin is functioning as inputs/outputs of SCI. In
other states, PBIORL is disabled. PBIORH is enabled when the port B pins are functioning as
general-purpose inputs/outputs (PB16). In other states, PBIORH is disabled.
A given pin on port B will be an output pin if the corresponding bit in PBIORH or PBIORL is set
to 1, and an input pin if the bit is cleared to 0.
However, bit 2 of PBIORL and bit 0 of PBIORH are disabled in SH7124.
Bits 15 to 6, 4, and 0 of PBIORL and bits 15 to 1 of PBIORH are reserved. These bits are always
read as 0. The write value should always be 0.
The initial value of PBIORL and PBIORH are H'0000, respectively.
• Port B I/O Register H (PBIORH)
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PB16
IOR
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R R/W
• Port B I/O Register L (PBIORL)
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
PB5
IOR
-
PB3 PB2 PB1
IOR IOR IOR
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R R/W R R/W R/W R/W R
Rev. 4.00 Jul. 25, 2008 Page 533 of 750
REJ09B0243-0400