SH7125_08 Datasheet, PDF (135/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 7 User Break Controller (UBC)
7.2 Register Descriptions
The user break controller has the following registers. For details on register addresses and register
states during each processing, refer to section 20, List of Registers.
Table 7.1 Register Configuration
Register Name
Abbrevia-
tion
R/W Initial Value Address
Access Size
Break address register A
BARA
R/W H'00000000 H'FFFFF300 32
Break address mask register A BAMRA R/W H'00000000 H'FFFFF304 32
Break bus cycle register A
BBRA
R/W H'0000
H'FFFFF308 16
Break data register A
BDRA
R/W H'00000000 H'FFFFF310 32
Break data mask register A BDMRA R/W H'00000000 H'FFFFF314 32
Break address register B
BARB
R/W H'00000000 H'FFFFF320 32
Break address mask register B BAMRB R/W H'00000000 H'FFFFF324 32
Break bus cycle register B
BBRB
R/W H'0000
H'FFFFF328 16
Break data register B
BDRB
R/W H'00000000 H'FFFFF330 32
Break data mask register B BDMRB R/W H'00000000 H'FFFFF334 32
Break control register
BRCR
R/W H'00000000 H'FFFFF3C0 32
Branch source register
BRSR
R
H'0xxxxxxx H'FFFFF3D0 32
Branch destination register BRDR
R
H'0xxxxxxx H'FFFFF3D4 32
Execution times break register BETR
R/W H'0000
H'FFFFF3DC 16
Rev. 4.00 Jul. 25, 2008 Page 115 of 750
REJ09B0243-0400