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SH7125_08 Datasheet, PDF (638/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family
Section 17 Flash Memory
(3) Erasing Procedure in User Program Mode
The procedures for download, initialization, and erasing are shown in figure 17.12.
Start erasing procedure
program
Select on-chip program
to be downloaded and
set download destination
by FTDAR
(3.1)
Set FKEY to H'A5
After clearing VBR,
set SCO to 1 and
execute download
Clear FKEY to 0
DPFR = 0?
Yes
No
Download error processing
Set the FPEFEQ and
FUBRA parameters
Initialization
JSR FTDAR setting + 32
FPFR = 0 ?
No
Yes Initialization error processing
1
1
Set FKEY to H'5A
Set FEBS parameter
(3.2)
Erasing
JSR FTDAR setting + 16 (3.3)
FPFR = 0 ?
(3.4)
No
Yes Clear FKEY and erasing
error processing
No
Required block
erasing is
completed?
(3.5)
Yes
Clear FKEY to 0
(3.6)
End erasing
procedure program
Figure 17.12 Erasing Procedure
The details of the erasing procedure are described below. The procedure program must be
executed in an area other than the user MAT to be erased.
Especially the part where the SCO bit in FCCS is set to 1 for downloading must be executed in
on-chip RAM.
Specify 1/4 (initial value) as the frequency division ratios of an internal clock (Iφ), a bus clock
(Bφ), and a peripheral clock (Pφ) through the frequency control register (FRQCR).
After the programming/erasing program has been downloaded and the SCO bit is cleared to 0,
the setting of the frequency control register (FRQCR) can be changed to the desired value. For
the downloaded on-chip program area, see the RAM map for programming/erasing in figure
17.10.
Rev. 4.00 Jul. 25, 2008 Page 618 of 750
REJ09B0243-0400