SH7125_08 Datasheet, PDF (641/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 17 Flash Memory
17.6.2 Software Protection
Software protection is set up in any of two ways: by disabling the downloading of on-chip
programs for programming and erasing and by means of a key code.
Table 17.9 Software Protection
Item
Protection by the
SCO bit
Protection by FKEY
Function to be Protected
Description
Download
Programming/
Erasure
Clearing the SCO bit in FCCS disables √
√
downloading of the programming/erasing
program, thus making the LSI enter a
programming/erasing-protected state.
Downloading and programming/erasing √
√
are disabled unless the required key code
is written in FKEY. Different key codes are
used for downloading and for
programming/erasing.
17.6.3 Error Protection
Error protection is a mechanism for aborting programming or erasure when an error occurs, in the
form of the microcomputer getting out of control during programming/erasing of the flash
memory or operations that are not in accordance with the established procedures for
programming/erasing. Aborting programming or erasure in such cases prevents damage to the
flash memory due to excessive programming or erasing.
If the microcomputer malfunctions during programming/erasing of the flash memory, the FLER
bit in FCCS is set to 1 and the LSI enters the error protection state, thus aborting programming or
erasure.
The FLER bit is set to 1 in the following conditions:
• When the relevant bank area of flash memory is read during programming/erasing (including a
vector read or an instruction fetch)
• When a SLEEP instruction (including software standby mode) is executed during
programming/erasing
Error protection is cancelled (FLER bit is cleared) only by a power-on reset.
Rev. 4.00 Jul. 25, 2008 Page 621 of 750
REJ09B0243-0400