SH7125_08 Datasheet, PDF (147/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 7 User Break Controller (UBC)
7.2.11 Break Control Register (BRCR)
BRCR sets the following conditions:
1. Channels A and B are used in two independent channel conditions or under the sequential
condition.
2. A break is set before or after instruction execution.
3. Specify whether to include the number of execution times on channel B in comparison
conditions.
4. Determine whether to include data bus on channels A and B in comparison conditions.
5. Enable PC trace.
6. Specify whether to request the user break interrupt when channels A and B match with
comparison conditions.
BRCR is a 32-bit readable/writable register that has break conditions match flags and bits for
setting a variety of break conditions.
Bit: 31 30 29 28 27 26 25
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
SCM
FCA
SCM
FCB
SCM
FDA
SCM
FDB
PCTE PCBA
-
Initial value: 0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R
24 23 22 21 20 19 18 17 16
-
-
-
-
- UBIDB - UBIDA -
0
0
0
0
0
0
0
0
0
R
R
R
R
R R/W R R/W R
8
7
6
5
4
3
2
- DBEA PCBB DBEB -
SEQ
-
0
0
0
0
0
0
0
R R/W R/W R/W R R/W R
1
0
- ETBE
0
0
R R/W
Initial
Bit
Bit Name Value R/W Description
31 to 20 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
19
UBIDB
0
R/W User Break Disable B
Enables or disables the user break interrupt request
when the channel B break conditions are satisfied.
0: User break interrupt request is enabled when break
conditions are satisfied
1: User break interrupt request is disabled when break
conditions are satisfied
Rev. 4.00 Jul. 25, 2008 Page 127 of 750
REJ09B0243-0400