SH7125_08 Datasheet, PDF (219/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2)
• TSR_5
Bit: 7
6
5
4
3
2
1
0
-
-
-
-
- CMFU5 CMFV5 CMFW5
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R R/(W)*¹ R/(W)*¹ R/(W)*¹
Note: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
Bit
Bit Name
7 to 3 —
2
CMFU5
Initial
Value
All 0
0
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/(W)*¹ Compare Match/Input Capture Flag U5
Status flag that indicates the occurrence of TGRU_5
input capture or compare match.
[Setting conditions]
• When TCNTU_5 = TGRU_5 and TGRU_5 is
functioning as output compare register
• When TCNTU_5 value is transferred to TGRU_5 by
input capture signal and TGRU_5 is functioning as
input capture register
• When TCNTU_5 value is transferred to TGRU_5 and
TGRU_5 is functioning as a register for measuring the
pulse width of the external input signal. The transfer
timing is specified by the IOC bits in timer I/O control
register U_5 (TIORU_5)*²
[Clearing condition]
• When 0 is written to CMFU5 after reading CMFU5 = 1
Rev. 4.00 Jul. 25, 2008 Page 199 of 750
REJ09B0243-0400