SH7125_08 Datasheet, PDF (690/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 19 Power-Down Modes
19.3.7 RAM Control Register (RAMCR)
RAMCR is an 8-bit readable/writable register that enables/disables the access to the on-chip
RAM.
Bit: 7
6
5
4
3
2
1
0
-
-
- RAME -
-
-
-
Initial value: 0
0
0
1
0
0
0
0
R/W: R
R
R R/W R
R
R
R
Bit
7 to 5
4
3 to 0
Bit Name

Initial
Value
All 0
RAME
1

All 0
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
R/W RAM Enable
This bit enables/disables the on-chip RAM.
0: On-chip RAM disabled
1: On-chip RAM enabled
When this bit is cleared to 0, the access to the on-chip
RAM is disabled. In this case, an undefined value is
returned when reading or fetching the data or
instruction from the on-chip RAM, and writing to the on-
chip RAM is ignored.
When RAME is cleared to 0 to disable the on-chip
RAM, an instruction to access the on-chip RAM should
not be set next to the instruction to write RAMCR. If
such an instruction is set, normal access is not
guaranteed.
When RAME is set to 1 to enable the on-chip RAM, an
instruction to read RAMCR should be set next to the
instruction to write to RAMCR. If an instruction to
access the on-chip RAM is set next to the instruction to
write to RAMCR, normal access is not guaranteed.
R Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 4.00 Jul. 25, 2008 Page 670 of 750
REJ09B0243-0400