SH7125_08 Datasheet, PDF (376/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2)
Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted
in Reset-Synchronized PWM Mode: Figure 9.129 shows an explanatory diagram of the case
where an error occurs in normal mode and operation is restarted in reset-synchronized PWM mode
after re-setting.
MTU2 module output
1
2
3
RESET TMDR TOER
(normal) (1)
4
5
6
TIOR PFC TSTR
(1 init (MTU2) (1)
0 out)
7
8
9
10
Match Error PFC TSTR
occurs (PORT) (0)
11
12
13
TIOR TIOR TOER
(0 init (disabled) (0)
0 out)
14
15
16
17
18
TOCR TMDR TOER PFC TSTR
(RPWM) (1) (MTU2) (1)
TIOC3A
TIOC3B
TIOC3D
Port output
PE8
PE9
High-Z
High-Z
PE11
High-Z
Figure 9.129 Error Occurrence in Normal Mode,
Recovery in Reset-Synchronized PWM Mode
1 to 13 are the same as in figure 9.124.
14. Select the reset-synchronized PWM output level and cyclic output enabling/disabling with
TOCR.
15. Set reset-synchronized PWM.
16. Enable channel 3 and 4 output with TOER.
17. Set MTU2 output with the PFC.
18. Operation is restarted by TSTR.
Rev. 4.00 Jul. 25, 2008 Page 356 of 750
REJ09B0243-0400