SH7125_08 Datasheet, PDF (436/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 12 Serial Communication Interface (SCI)
12.3.4 Transmit Data Register (SCTDR)
SCTDR is an 8-bit register that stores data for serial transmission. When the SCI detects that the
transmit shift register (SCTSR) is empty, it moves transmit data written in the SCTDR into
SCTSR and starts serial transmission. If the next transmit data has been written to SCTDR during
serial transmission from SCTSR, the SCI can transmit data continuously. SCTDR can always be
written or read to by the CPU.
Bit: 7
6
5
4
3
2
1
0
Initial value: -
-
-
-
-
-
-
-
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
12.3.5 Serial Mode Register (SCSMR)
SCSMR is an 8-bit register that specifies the SCI serial communication format and selects the
clock source for the baud rate generator.
The CPU can always read and write to SCSMR.
Bit: 7
C/A
Initial value: 0
R/W: R/W
6
CHR
0
R/W
5
PE
0
R/W
4
3
2
O/E STOP MP
0
0
0
R/W R/W R/W
1
0
CKS[1:0]
0
0
R/W R/W
Initial
Bit
Bit Name value R/W Description
7
C/A
0
R/W Communication Mode
Selects whether the SCI operates in asynchronous or
clock synchronous mode.
0: Asynchronous mode
1: Clock synchronous mode (Channel 1 in the SH7124
is not available.)
Rev. 4.00 Jul. 25, 2008 Page 416 of 750
REJ09B0243-0400