SH7125_08 Datasheet, PDF (361/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2)
MPφ
TCNT write cycle
T1 T2
Address
TCNT_2 address
Write signal
TCNT_2
TGRA_2 to
TGRB_2
Ch2 compare-
match signal A/B
TCNT_1 input
clock
TCNT_1
H'FFFE
H'FFFF
N
TCNT_2 write data
H'FFFF
Disabled
M
N+1
TGRA_1
Ch1 compare-
match signal A
TGRB_1
Ch1 input capture
signal B
TCNT_0
M
N
M
P
TGRA_0 to
TGRD_0
Ch0 input capture
signal A to D
Q
P
Figure 9.118 TCNT_2 Write and Overflow/Underflow Contention with Cascade
Connection
Rev. 4.00 Jul. 25, 2008 Page 341 of 750
REJ09B0243-0400