SH7125_08 Datasheet, PDF (435/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 12 Serial Communication Interface (SCI)
12.3.1 Receive Shift Register (SCRSR)
SCRSR receives serial data. Data input at the RXD pin is loaded into SCRSR in the order
received, LSB (bit 0) first, converting the data to parallel form. When one byte has been received,
it is automatically transferred to SCRDR. The CPU cannot read or write to SCRSR directly.
Bit: 7
6
5
4
3
2
1
0
Initial value: -
-
-
-
-
-
-
-
R/W: -
-
-
-
-
-
-
-
12.3.2 Receive Data Register (SCRDR)
SCRDR is a register that stores serial receive data. After receiving one byte of serial data, the SCI
transfers the received data from the receive shift register (SCRSR) into SCRDR for storage and
completes operation. After that, SCRSR is ready to receive data.
Since SCRSR and SCRDR work as a double buffer in this way, data can be received continuously.
SCRDR is a read-only register and cannot be written to by the CPU.
Bit: 7
6
5
4
3
2
1
0
Initial value: -
-
-
-
-
-
-
-
R/W: R
R
R
R
R
R
R
R
12.3.3 Transmit Shift Register (SCTSR)
SCTSR transmits serial data. The SCI loads transmit data from the transmit data register (SCTDR)
into SCTSR, and then transmits the data serially from the TXD pin, LSB (bit 0) first. After
transmitting one data byte, the SCI automatically loads the next transmit data from SCTDR into
SCTSR and starts transmitting again. If the TDRE flag in the serial status register (SCSSR) is set
to 1, the SCI does not transfer data from SCTDR to SCTSR. The CPU cannot read or write to
SCTSR directly.
Bit: 7
6
5
4
3
2
1
0
Initial value: -
-
-
-
-
-
-
-
R/W: -
-
-
-
-
-
-
-
Rev. 4.00 Jul. 25, 2008 Page 415 of 750
REJ09B0243-0400