SH7125_08 Datasheet, PDF (14/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

9.7.2 Input Clock Restrictions ....................................................................................... 332
9.7.3 Caution on Period Setting ..................................................................................... 333
9.7.4 Contention between TCNT Write and Clear Operations...................................... 333
9.7.5 Contention between TCNT Write and Increment Operations............................... 334
9.7.6 Contention between TGR Write and Compare Match .......................................... 335
9.7.7 Contention between Buffer Register Write and Compare Match ......................... 336
9.7.8 Contention between Buffer Register Write and TCNT Clear ............................... 337
9.7.9 Contention between TGR Read and Input Capture............................................... 338
9.7.10 Contention between TGR Write and Input Capture.............................................. 339
9.7.11 Contention between Buffer Register Write and Input Capture ............................. 340
9.7.12 TCNT_2 Write and Overflow/Underflow Contention in Cascade Connection .... 340
9.7.13 Counter Value during Complementary PWM Mode Stop .................................... 342
9.7.14 Buffer Operation Setting in Complementary PWM Mode ................................... 342
9.7.15 Reset Sync PWM Mode Buffer Operation and Compare Match Flag .................. 343
9.7.16 Overflow Flags in Reset Synchronous PWM Mode ............................................. 344
9.7.17 Contention between Overflow/Underflow and Counter Clearing......................... 345
9.7.18 Contention between TCNT Write and Overflow/Underflow................................ 346
9.7.19 Cautions on Transition from Normal Operation or PWM Mode 1
to Reset-Synchronized PWM Mode ..................................................................... 346
9.7.20 Output Level in Complementary PWM Mode
and Reset-Synchronized PWM Mode................................................................... 347
9.7.21 Interrupts in Module Standby Mode ..................................................................... 347
9.7.22 Simultaneous Capture of TCNT_1 and TCNT_2 in Cascade Connection............ 347
9.8 MTU2 Output Pin Initialization......................................................................................... 348
9.8.1 Operating Modes .................................................................................................. 348
9.8.2 Reset Start Operation ............................................................................................ 348
9.8.3 Operation in Case of Re-Setting Due to Error During Operation, etc. ................. 349
9.8.4 Overview of Initialization Procedures
and Mode Transitions in Case of Error during Operation, etc. ............................. 350
Section 10 Port Output Enable (POE) ............................................................... 381
10.1 Features.............................................................................................................................. 381
10.2 Input/Output Pins............................................................................................................... 383
10.3 Register Descriptions ......................................................................................................... 384
10.3.1 Input Level Control/Status Register 1 (ICSR1) .................................................... 385
10.3.2 Output Level Control/Status Register 1 (OCSR1) ................................................ 388
10.3.3 Input Level Control/Status Register 3 (ICSR3) .................................................... 389
10.3.4 Software Port Output Enable Register (SPOER) .................................................. 391
10.3.5 Port Output Enable Control Register 1 (POECR1)............................................... 393
10.3.6 Port Output Enable Control Register 2 (POECR2)............................................... 394
Rev. 4.00 Jul. 25, 2008 Page xiv of xx