SH7125_08 Datasheet, PDF (438/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 12 Serial Communication Interface (SCI)
Initial
Bit
Bit Name value R/W Description
3
STOP
0
R/W Stop Bit Length
Selects one or two bits as the stop bit length in
asynchronous mode. This setting is used only in
asynchronous mode. It is ignored in clock synchronous
mode because no stop bits are added.
0: One stop bit*¹
1: Two stop bits*²
When receiving, only the first stop bit is checked,
regardless of the STOP bit setting. If the second stop
bit is 1, it is treated as a stop bit, but if the second stop
bit is 0, it is treated as the start bit of the next incoming
character.
Notes: 1. When transmitting, a single 1-bit is added at
the end of each transmitted character.
2. When transmitting, two 1 bits are added at the
end of each transmitted character.
2
MP
0
R/W Multiprocessor Mode (only in asynchronous mode)
Enables or disables multiprocessor mode. The PE and
O/E bit settings are ignored in multiprocessor mode.
0: Multiprocessor mode disabled
1: Multiprocessor mode enabled
1, 0
CKS[1:0] 00
R/W Clock Select 1 and 0
Select the internal clock source of the on-chip baud rate
generator. Four clock sources are available. Pφ, Pφ/4,
Pφ/16 and Pφ/64. For further information on the clock
source, bit rate register settings, and baud rate, see
section 12.3.10, Bit Rate Register (SCBRR).
00: Pφ
01: Pφ/4
10: Pφ/16
11: Pφ/64
Note: Pφ: Peripheral clock
Rev. 4.00 Jul. 25, 2008 Page 418 of 750
REJ09B0243-0400