SH7125_08 Datasheet, PDF (39/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 2 CPU
2.2.1 General Registers (Rn)
There are sixteen 32-bit general registers (Rn), designated R0 to R15. The general registers are
used for data processing and address calculation. R0 is also used as an index register. With a
number of instructions, R0 is the only register that can be used. R15 is used as a hardware stack
pointer (SP). In exception handling, R15 is used for accessing the stack to save or restore the
status register (SR) and program counter (PC) values.
2.2.2 Control Registers
There are three 32-bit control registers, designated status register (SR), global base register
(GBR), and vector base register (VBR). SR indicates a processing state. GBR is used as a base
address in GBR indirect addressing mode for data transfer of on-chip peripheral module registers.
VBR is used as a base address of the exception handling (including interrupts) vector table.
• Status register (SR)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
-
-
-
-
-
-
M
Q
I[3:0]
-
Initial value: 0
0
0
0
0
0
-
-
1
1
1
1
0
R/W: R
R
R
R
R
R R/W R/W R/W R/W R/W R/W R
2
1
0
-
S
T
0
-
-
R R/W R/W
Bit
31 to 10
9
8
7 to 4
3, 2
Bit
name

Default
All 0
M
Q
I[3:0]

Undefined
Undefined
1111
All 0
Read/
Write
R
R/W
R/W
R/W
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Used by the DIV0U, DIV0S, and DIV1 instructions.
Used by the DIV0U, DIV0S, and DIV1 instructions.
Interrupt Mask
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 4.00 Jul. 25, 2008 Page 19 of 750
REJ09B0243-0400