SH7125_08 Datasheet, PDF (418/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 10 Port Output Enable (POE)
10.4.2 Output-Level Compare Operation
Figure 10.4 shows an example of the output-level compare operation for the combination of
TIOC3B and TIOC3D. The operation is the same for the other pin combinations.
Pφ
PE9/
TIOC3B
PE11/
TIOC3D
Low level overlapping detected
High impedance state
Figure 10.4 Output-Level Compare Operation
10.4.3 Release from High-Impedance State
High-current pins that have entered high-impedance state due to input-level detection can be
released either by returning them to their initial state with a power-on reset, or by clearing all of
the flags in bits 12 to 15 (POE0F to POE3F and POE8F) in ICSR1. However, note that when low-
level sampling is selected by bits 0 to 7 in ICSR1, just writing 0 to a flag is ignored (the flag is not
cleared); flags can be cleared by writing 0 to it only after a high level is input to the POE pin and
is sampled.
High-current pins that have entered high-impedance state due to output-level detection can be
released either by returning them to their initial state with a power-on reset, or by clearing the flag
in bit 15 (OCF1) in OCSR1. However, note that just writing 0 to a flag is ignored (the flag is not
cleared); flags can be cleared only after an inactive level is output from the high-current pins.
Inactive-level outputs can be achieved by setting the MTU2 internal registers.
Rev. 4.00 Jul. 25, 2008 Page 398 of 750
REJ09B0243-0400