SH7125_08 Datasheet, PDF (529/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 14 Compare Match Timer (CMT)
14.4 Interrupts
14.4.1 CMT Interrupt Sources
The CMT has channels and each of them to which a different vector address is allocated has
compare match interrupt. When both the interrupt request flag (CMF) and interrupt enable bit
(CMIE) are set to 1, the corresponding interrupt request is output. When the interrupt is used to
activate a CPU interrupt, the priority of channels can be changed by the interrupt controller
settings. For details, see section 6, Interrupt Controller (INTC).
14.4.2 Timing of Setting Compare Match Flag
When CMCOR and CMCNT match, a compare match signal is generated and the CMF bit in
CMCSR is set to 1. The compare match signal is generated in the last cycle in which the values
match (when the CMCNT value is updated to H'0000). That is, after a match between CMCOR
and CMCNT, the compare match signal is not generated until the next CMCNT counter clock
input. Figure 14.4 shows the timing of CMF bit setting.
Peripheral operating
clock (Pφ)
Counter clock
(N + 1)th
clock
CMCNT
N
0
CMCOR
N
Compare match
signal
Figure 14.4 Timing of CMF Setting
14.4.3 Timing of Clearing Compare Match Flag
The CMF bit in CMCSR is cleared by reading 1 from this bit, then writing 0.
Rev. 4.00 Jul. 25, 2008 Page 509 of 750
REJ09B0243-0400