SH7125_08 Datasheet, PDF (152/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 7 User Break Controller (UBC)
7.2.13 Branch Source Register (BRSR)
BRSR is a 32-bit read-only register. BRSR stores bits 27 to 0 in the address of the branch source
instruction. BRSR has the flag bit that is set to 1 when a branch occurs. This flag bit is cleared to 0
by a power-on reset or manual reset when BRSR is read or the setting to enable PC trace is made.
Other bits are not initialized by a power-on reset. The eight BRSR registers have a queue structure
and a stored register is shifted at every branch.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SVF
-
-
- BSA27 BSA26 BSA25 BSA24 BSA23 BSA22 BSA21 BSA20 BSA19 BSA18 BSA17 BSA16
Initial value: 0
0
0
0
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
BSA15 BSA14 BSA13 BSA12 BSA11 BSA10 BSA9 BSA8 BSA7 BSA6 BSA5 BSA4 BSA3 BSA2 BSA1 BSA0
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit
Bit Name
31
SVF
30 to 28 
27 to 0 BSA27 to
BSA0
Initial
Value R/W
0
R
All 0
R
Undefined R
Description
BRSR Valid Flag
Indicates whether the branch source address is stored.
This flag bit is set to 1 when a branch occurs. This flag
is cleared to 0 when BRSR is read, the setting to
enable PC trace is made, or BRSR is initialized by a
power-on reset.
0: The value of BRSR register is invalid
1: The value of BRSR register is valid
Reserved
These bits are always read as 0. The write value
should always be 0.
Branch Source Address
Store bits 27 to 0 of the branch source address.
Rev. 4.00 Jul. 25, 2008 Page 132 of 750
REJ09B0243-0400